`timescale 1ns/1ns

module phy_reg_config_tb;

	reg clk;
	reg rst_n;
	wire mdio;
	wire mdc;
	wire phy_rst_n;
	wire [15:0] rddata;
	wire phy_init_done;

	pullup PUP(mdio);
	
	phy_reg_config	phy_reg_config_inst(
		.clk					(clk				),	//模块时钟50MHz
		.rst_n					(rst_n				),	//模块复位，低电平有效
		.mdio					(mdio				),	//管理接口数据总线
		.mdc					(mdc				),	//管理接口时钟总线
		.phy_rst_n				(phy_rst_n			),	//phy芯片复位，低电平有效
		.rddata					(rddata				),	//从phy寄存器读出的16位数据
		.phy_init_done			(phy_init_done		)	//phy寄存器初始化操作完成标志
	);
	
	initial clk = 1;
	always #10 clk =~clk;
	
	initial begin
	rst_n = 0;
	#201;
	rst_n = 1;
	@(posedge phy_init_done)
	#2000;
	//$stop;
	end

endmodule 